The invention relates to Intel processor based personal computer hardware implementations, and particularly to SMRAM support for Intel processors employing System Management Mode.
Computer systems employing the SL Enhanced Intel486.TM. microprocessor (and follow-ons) can take advantage of an operating mode unique to that architecture and known as "System Management Mode" (SMM). SMM can be used by the system firmware to control product-specific hardware features in a manner which is transparent to the Operating System and applications software. SMM may be used, for example, for system management information such as the system configuration or the configuration of a powered-down device, or to invoke a power-saving routine such as a zero-volt suspend function.
SMM is, however, subject to certain inefficiencies in DOS.TM. compatible personal computer systems. When operating in SMM, the Intel microprocessor accesses a dedicated memory known as SMRAM. SMRAM can be implemented in one of two ways. First of all, SMRAM can occupy an area of memory having a uniquely addressable location--known as "non-overlayed" memory. In such an arrangement, SMRAM is fully cacheable in the processor's internal cache. However, in DOS compatible systems, the first megabyte of memory space is mapped according to software compatibility requirements, forcing SMRAM to be located beyond the first megabyte of addressable memory space. But operating from memory spaces beyond the first megabyte has certain restrictions associated with it according to the processor architecture--in particular, far jumps are restricted and code size is constrained to 64K segments.
Therefore a second SMRAM implementation is more typically used in personal computer system designs. Accordingly, SMRAM is addressed such that it overlays some other area of system memory in the first megabyte--that is, it is addressed at the same location as the other area. When the processor is in normal mode, accesses to that location of system memory are treated normally. When in SMM, accesses to that location are redirected to SMRAM. The processor is unaware of the remapping.
Because the processor is unaware of the remapping, its internal cache cannot differentiate between the two physically separate memories. Cache coherency is thus compromised. This problem is currently approached in either of two ways: by making SMRAM non-cacheable, or by doing cache invalidate cycles upon entry and exit from SMM. Both of these schemes negatively impact performance by making ineffective use of the cache.
As SMM applications expand they continue to demand greater proportions of processor time. Thus, there is an increasing need for a more efficient SMRAM implementation.